1. Field of the Invention
The present invention relates to techniques for forming metal fuses in CMOS processes with copper. More particularly, the present invention relates to forming metal fuses in device structures having copper interconnect layers.
2. Description of the Related Art
As semiconductor devices, such as integrated circuit chips, continue to decrease in size and increase in complexity, the likelihood of a defective chip resulting from a failed element or a defective conductor increases. One way to reduce the number of chips which must be discarded due to fabrication defects is to manufacture fuses into semiconductor devices. Fuses may be opened to isolate defective areas and allow the rest of the circuit on a chip to be used. Fuses may also be used to trim a circuit, enable a particular mode, or enable or disable different segments of a circuit.
One example of the use of fuses in semiconductor devices is the provision of redundant elements on integrated circuits. If a primary element is defective a redundant element can be substituted for that defective element, rather than discarding the chip. An example of a semiconductor device which uses redundant elements is electronic memory. Typical memory chips are composed of millions of equivalent memory cells arranged in addressable rows and columns. Semiconductor memory chips are typically fabricated with built-in redundancy in case one or more bits are found to be bad after fabrication. If a bad bit is found in testing following fabrication, fuses may be blown to xe2x80x9cprogramxe2x80x9d a redundant cell to respond to the address of the defective primary cell. The use of the redundant rows and columns in memory cells increases economic efficiency by substantially raising yields. That is, an entire chip need not be rejected in the event that only a few bits of memory are bad since those bad bits may be replaced by the redundancy built into the chip.
Recently, redundancy circuits employing fuses have been applied in Application Specific Integrated Circuits (xe2x80x9cASIC""sxe2x80x9d) with larger amounts of embedded memory. Embedded memory is a combination of memory and logic on the same chip formed during the same fabrication process. For example, an embedded memory cell may include a single silicon layer processed to form transistor devices for both logic and memory functions covered by a series of metal layers which provide routing and interconnects to the silicon layer. Embedded memory cell arrays typically have, for example, two to six metal layers. Since the silicon logic and memory layer is overlaid by metal layers in an embedded memory cell device, it is preferred to use fuses in an upper metal layer to disable bad bits or enable redundant bits built into an embedded memory array. Redundancy is built into embedded memory arrays for the same reason as stand-alone memory, that is, to increase economic efficiency by increasing yield.
The conventional approach in using a laser to blow such fuses is to irradiate the fuse with a pulsed laser beam whose energy density and pulse duration are sufficient to vaporize the fuse material, thereby severing the electrical link. As a result of the process of blowing the filses, in conventional methods, the fuse and the surrounding dielectric layer may be exposed to the atmosphere.
The ongoing miniaturization of devices presents new problems in forming and blowing fuses. The scaling of semiconductor devices has resulted in some shifting to the use of copper interconnects and low-k dielectric materials to increase circuit and chip performance by reducing interconnect resistance and capacitance. However, copper readily oxidizes in a non self-limited reaction when exposed to air, such as may occur when the fuse is blown. This can lead to regrowth of blown copper fuses (i.e. an unintended rejoining of the severed ends of a copper fuse) causing the chip to fail. Low-k materials are porous and easily absorb moisture from air. If, after blowing the metal fuse the low-k material is exposed, excess moisture absorption may ultimately cause the chip to fail.
Moreover, power supply scaling may result in a device structure having one or more thick metal redistribution layers to efficiently distribute power across the chip while minimizing the voltage drop along the power lines. Generally it is advisable to have thick redistribution metal layers to avoid a voltage drop from the periphery to the center of the chip. However, these thick redistribution layers may be unsuitable for use in the formation of metal fuses. Redistribution layers, for example, may be about 1.0 to 3.0 microns in thickness and preferably between 1.5 and 3.0 microns in 0.13 micron device technology, thus making it difficult to blow the fuse without exceeding the thermal capacity of the device. Typical processing methods use copper for all metal layers except for the pad metal. Copper""s high thermal conductance characteristic requires greater heat to blow the fuse than a same thickness fuse made from other metals such as aluminum.
Although fuses have conventionally been placed in some layer below the topmost metal layer, the addition of one or more dielectric layers and one or more redistribution layers placed above the top-most metal layer create additional difficulties in producing a fuse which will reliably blow. The thickness of the conductors in the redistribution layers makes them unsuitable for fuse formation due to the high thermal conductance of copper.
The thickness of the dielectric on top of the fuse portion to be blown is desirably optimized so that the dielectric at that location absorbs the maximum incident laser energy, allowing the fuse to blow more easily. This is conventionally accomplished by partially etching the dielectric layers over the fuse to create an opening over the fuse area to be blown. However, adding one or more redistribution layers adds one or more dielectric layers which must be etched in order to create the window to a desired depth.
For example, FIG. 1 depicts a semiconductor device having a fuse 109 formed by conventional techniques. A first layer of low k dielectric material 102 is placed over a portion of the integrated circuit device. xe2x80x9cLow k dielectric materialxe2x80x9d refers to a dielectric material having a dielectric constant k which is below the dielectric constant of silicon dioxide (SiO2). Preferably this low k value is below 3.5 and most preferably below 3.0. In the upper surface of the low-k dielectric material 102 an opening is etched and later filled with a filler material such as copper to form metal layer (MT-1) 104. Fuse 109 may be formed in this same metal layer according to the same technique. A process step such as chemical mechanical polishing (xe2x80x9cCMPxe2x80x9d) planarizes the surface 105 in preparation for deposition of additional layers. A second low-k dielectric material 106 is then deposited on the planarized surface 105 of the combined layers 102 and 104 to enable formation of a top metal layer 108. The top metal layer 108 is formed by methods similar to those used in the formation of the metal layer 104 described above, i.e. by damascene etching followed by depositing a filler metal such as copper, and planarizing the surface 111. A dielectric material 112 is then deposited. Fluorinated silicate glass (xe2x80x9cFSGxe2x80x9d) is commonly used for this dielectric layer 112. FSG may be formed by doping SiO2 with fluoride to reduce its k value to approximately 3.6. Openings are etched into the upper surface of the dielectric layer 112 and filled with a filler metal such as copper to form redistribution layer 114. The redistribution metal layer 114 and dielectric 112 are planarized using conventional CMP procedures. The embodiments of the present invention may use these steps or other conventional steps to form a partially completed semiconductor device up to and including a redistribution metal layer The remaining stages using conventional techniques will be further described to highlight some of the problems created using conventional techniques. Subsequently a second dielectric layer 118 is deposited on the redistribution metal layer 114. After patterning and etching the second dielectric layer 118 to form opening 123, a conductive barrier layer 116 is deposited in the opening 123 and on the second dielectric layer 118. Subsequently metal pad layer 120 is deposited using a metal such as aluminum. Both metal pad layers 116 and 120 are patterned and etched to form the final configuration of metal pad 120. Separately, opening 122 is formed by initially patterning and etching second dielectric layer 118, followed by etching of layers 112 and 106. In conventional processes, the depth of the opening 122 is accurately controlled in order to provide an optimal thickness for the dielectric overlying the portion of the fuse to be blown. However, the dielectric thickness presented by the multiple layers makes it difficult to accurately control the depth of the opening 122 and thus the thickness 124 of the dielectric over the fuse. Thus conventional methods for forming copper fuses may not produce a fuse that will reliably blow, especially when one or more metal redistribution layers are incorporated into the device.
Accordingly, it is desirable to produce a semiconductor fuse that will reliably blow in a device having copper interconnects, low-k dielectric layers, or a redistribution layer.
To achieve the foregoing, the present invention provides a method of forming a semiconductor device fuse and a semiconductor device fuse structure. A first dielectric layer is formed on top of a metal layer in a semiconductor device. The dielectric layer is patterned to provide access to fuse contacts located in one of the metal layers. A conductive pad metal layer is deposited and patterned to form a fuse between the fuse contacts. A second dielectric layer is deposited on the patterned conductive pad metal layer. This method permits fuses to be formed in the pad metal layer where the thickness of the dielectric over the area of the fuse to be blown may be more easily controlled.
In one aspect, the invention provides a method of forming a semiconductor device fuse. A first dielectric layer is deposited on the top-most copper metal layer in the device. The first dielectric is patterned to provide access to at least two fuse contacts. A conductive metal layer is deposited and patterned to form a fuse connecting the at least two fuse contact holes. A second dielectric layer is deposited on the patterned conductive layer.
In another aspect, the conductive metal layer is deposited and patterned to form a metal pad and a fuse connecting the at least two fuse contacts.
In yet another aspect a semiconductor device having a fuse is provided. The device comprises a first dielectric layer disposed on top of a top interconnect layer in the device. The first dielectric layer has an opening providing access to at least two fuse contacts. A fuse is formed in the pad metal layer and connects the at least two fuse contacts. A second dielectric layer is disposed on at least a portion of the fuse material in the pad metal layer.
These and other features and advantages of the present invention are described below with reference to the drawings.